The present invention relates to a method for fabricating a semiconductor device, more specifically to a method for fabricating a semiconductor device including a floating gate.
As larger scale, higher integration, and higher performance are recently required of LSIs, semiconductor devices themselves are further micronized. For higher integration of a semiconductor device, micronization of not only the semiconductor device itself, but also of a device isolation region defining a device region are important.
As the device isolation method, the so-called LOCOS (LOCal Oxidation of Silicon) method which thermally oxidizes a silicon substrate with silicon nitride film as a mask to locally form oxide film has been conventionally used.
In LOCOS technique, however, oxygen is diffused also below the silicon nitride film from the edges of a pattern of the silicon nitride film to form the so-called a bird's beak. The device isolation film intrudes into the device region by a length of the bird's beak. The length of the bird's beak is longer as the device isolation film is thicker. For further micronization of a device, it is preferable to make the device isolation film as thin as possible.
On the other hand, a semiconductor device including a floating gate, such as a flash EEPROM, EPROM or others, requires high voltage for write/erase of a memory cell. However, it is difficult to reduce the voltage for the write-erase, which makes it difficult to make the device isolation film for a peripheral circuit region for increase to the high voltage.
To satisfy these contradictory ends, in a semiconductor device, such as a flash EEPROM, EPROM or others, it is common that a thin device isolation film is formed in a memory cell region especially requiring integration, and a thick device isolation film is formed in a peripheral circuit region requiring high voltage resistance.
An example that a method for fabricating a semiconductor device, in which device isolation films which are different in thickness from each other are formed by LOCOS technique is applied to a semiconductor device including a floating gate will be explained.
FIG. 16 shows one example of the mask layout on a peripheral edge of a memory cell including a floating gate. In FIG. 16, the upper left part of the SAE mask substantially corresponds to the memory cell region, and the lower right part of the SAE mask substantially corresponds to the peripheral circuit region.
First, a silicon nitride film is deposited on a silicon substrate through a pad oxide film.
Then, the silicon nitride film in the peripheral circuit region where the thick device isolation film is to be formed is selectively removed. Then, the silicon nitride film in the memory cell region where the thinner device isolation film is to be formed is not removed. The mask used in patterning the silicon nitride film will be hereinafter called "S/D (source/drain) mask".
Subsequently, with the silicon nitride film as a mask, the silicon substrate is thermally oxidized to form an oxide film of a required thickness in the peripheral circuit region.
Then, the silicon nitride film in the memory cell region is selectively removed. The silicon nitride film will remain only in a region which is to be the device region. The mask for patterning the silicon nitride film will be hereinafter called "Core S/D (core source/drain) mask".
Then, the silicon substrate is thermally oxidized with the silicon nitride film as a mask. In this oxidation, the device isolation film is formed by the two steps of oxidation in the peripheral circuit region where the oxide film of a required thickness has been formed. Thus, a thin device isolation film is formed in the memory cell region, and a thick device isolation film is formed in the peripheral circuit region.
Then, the silicon nitride film remaining in the device region is removed.
Next, a silicon oxide film which is to be a tunnel oxide film of a memory cell transistor is formed in the device region.
Then, a polycrystalline silicon film which is to be a floating gate is formed on the entire surface, and the polycrystalline silicon film in the memory cell region is processed in a prescribed pattern. At this time, the entire peripheral circuit region is covered with the polycrystalline silicon film. The mask for patterning the polycrystalline silicon film will be hereinafter called "Poly 1 mask".
Subsequently an ONO film (a laminated film of the silicon nitride film sandwiched by the silicon oxide film) which is an insulation film between the floating gate and a control gate is formed.
Then, the ONO film and the polycrystalline silicon film in the peripheral circuit region are removed. The mask for patterning the ONO film and the polycrystalline silicon film will be hereinafter called "ONO mask".
Next, a silicon oxide film which is to be a gate insulation film of a transistor for a peripheral circuit is formed.
Subsequently, a laminated film of a polycrystalline silicon film and a tungsten silicide film is deposited and patterned to form the control gate in the memory cell region and a gate electrode of the transistor for a peripheral circuit in the peripheral circuit region. The mask for patterning the control gate will be hereinafter called "Poly 2 mask".
Then, a photoresist covering the peripheral circuit region is formed, and the ONO film and the polycrystalline silicon film are patterned with the control gate as a mask. Thus, the floating gate which has been formed below the control gate through the insulation film is in alignment with the control gate. The mask for patterning the floating gate will be hereinafter called "SAE (Self Align Etch) mask".
The semiconductor device including the floating gate has been thus fabricated.
However, in the above-described conventional method for fabricating a semiconductor device, residue of the ONO film and the polycrystalline silicon film often is left on steps formed in the device isolation films, etc.
Causes for the residue will be explained.
FIG. 17 is sectional views of the semiconductor device in the steps of the method for fabricating the same, which explain disadvantages of the same.
In the layout shown in FIG. 16, the S/D mask for forming the thick device isolation film is formed inner of the memory cell than the Core S/D for patterning the thin device isolation film.
In this layout, because none of the silicon nitride film remains in the region (shaded) enclosed by the Core S/D mask and the S/D mask when the silicon nitride film is etched by using the Core S/D as the mask, the oxide film 20 which is to be the thick device isolation film 24 is etched at the same time of the etching of the silicon nitride film to form a step at their border (FIG. 17A to 17B).
Because of a step thus formed in the device isolation film 24, when the ONO film 32 and the polycrystalline silicon film 30 are removed by anisotropic etching using the ONO mask, often the ONO film 32 is not completely removed and remain on the step. With the ONO film 32 remaining on the step, the etching of the base polycrystalline silicon film 30 goes on with the ONO film 32 as the mask, and often residue of the polycrystalline silicon film 30 remains on the step (FIGS. 17C to 17D).
It is an idea to remove the residue by overetching, but it is difficult to remove the residue by overetching in a region having steps generated by various fabrication steps as shown in FIG. 16.
Also by removing the ONO film 32 by isotropic etching the residue can be decreased, but it is difficult to uniformly etch the ONO film 32, which is a layer of the films having etching characteristics different from each other.
The ONO film 32 is deposited also on the sidewall of the polycrystalline silicon film 30 etched, using the Poly 1 mask (FIG. 17D). Accordingly, the ONO film 32 remains in this region even after the ONO film 32 and the polycrystalline silicon film 30 are removed, using the ONO mask (FIG. 17E).
To remove the ONO film 32, it is necessary to overetch the ONO film 32 by a thickness of the polycrystalline silicon film 30. When the ONO film 32 remains as residue 50, there is a risk that the residue 50 may peel to be particles in the self-alignment etching step of patterning the floating gate (the step of etching using the SAE mask).
However, the overetching sufficient to remove the ONO film 32 remarkably etches even the device isolation film 32 exposed on the surface, which makes it difficult to maintain the device isolation film 24 sufficiently thick. Especially in a region 54 with the control gate extended in to which a high voltage is to be applied, it is not preferable that the device isolation film 24 is made thin.
By laying the S/D mask outside the Core S/D mask as shown in FIG. 18, the formation of a step in the device isolation film 24 can be prevented. However, an active region is formed in the region 56 in FIG. 18, but none of the polycrystalline silicon film 30 of the same layer as the floating gate is formed on the region, so that the silicon substrate is dug in the etching step using the ONO mask and the etching step using the SAE mask. Accordingly, unpreferably the fabricating of the semiconductor device by the use of the layout of FIG. 18 has a risk that the surface planarization may be deteriorated, and the junction leak current is large. In addition, it is difficult to remove residue of a conducting film to be the control gate from the step formed in the region 56.